As DDR memory technology has increased its pace transferring from DDR3 to DDR4, the design of the physical layer complying DDR4 JEDEC has become essential to memory controller overall performance. This work presents the design of the transmitter block implementation inside the physical layer of the memory controller running with 3.2GHz. Detailed design have been analyzed for implementing the transmitter which is able to provide adjustable matched impedance with transmission line and meanwhile having the output swing complying the DDR4 JEDEC specification. Two impedance line models was used in the simulation. This work also conducts a comprehensive research of the current DDR4 technology in the aspect of industry trend, potential market size, potential customers, competitive technologies and intellectual property issues.
Title
Next Generation Memory Interfaces
Published
2015-05-14
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
EECS-2015-113
Type
Text
Extent
50 p
Archive
The Engineering Library
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