The last decade has witnessed a tremendous growth in wireless communications. Today's consumers demand wireless systems that are low-cost, power efficient, reliable and have a small form-factor. This quest for ubiquitous wireless connectivity and the trend toward highly integrated solutions have opened up a new wave of challenges and opportunities for RF (radio-frequency) integrated circuit design. Since it often dictates both battery life and form factor, the transmitter - and in particular the power amplifier (PA) - is often the most challenging block in this integrated radio design. The grand vision for wireless transmitters is to merge as many components as possible, if not all, into a single die in an inexpensive technology. There is therefore growing interest in utilizing CMOS technologies for power amplifiers (PAs). However, the low-supply voltage of nanoscale CMOS technology, the loss of on-chip passives and the conductive silicon substrate make a fully-integrated PA design challenging. This thesis focuses on the design of fully-integrated PAs for modern wireless communication systems at RF (2.4GHz) as well as 60GHz frequencies. Transformer based matching networks have been studied for PA design and new modeling methods proposed in this work. It has been shown that there is tremendous area benefit of using transformers at 60GHz, while still preserving high performance. A prototype of a transformer-coupled PA has been designed at 60GHz in 90nm CMOS technology. The transformer design and modeling proposed at 60GHz is equally valid at RF frequencies. However, the high output power and high linearity requirements at RF frequencies create further challenges. Conventional power amplifier architectures are showing limitations in terms of achievable efficiency and area reduction. In particular, such architectures are not benefiting much from technology scaling since the area is dominated by passive elements. In this thesis, we investigate a mixed-signal power amplifier architecture. By merging our work on transformer-coupled PAs with a digital signal processing framework, a truly scalable, efficient transmitter architecture can be created. Such a prototype has been designed and tested in 65nm CMOS technology.