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Ising machines have emerged as a new paradigm in unconventional computing that can solve NP-Hard problems. This report looks at both the hardware and algorithm design of these Ising machines. First we will take a look at the implementations of two different hardware accelerators. The first accelerator is a digitally-synthesized, Field Programmable Gate Array (FPGA) that performs synchronous Gibbs sampling of a Restricted Boltzmann Machine (RBM). The second accelerator is an asynchronous neural network that uses a mixed-analog signal neuron to drive stochastic local updates. On the algorithmic side, we explore mappings of the Travelling Salesman Problem. In particular, we introduce a Quadratic Unconstrained Binary Optimization (QUBO) mapping that uses the classical k-opt algorithm to perform local search.

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