Two techniques for spur and phase noise cancellation have been proposed. With analog- signal-processing by delay lines we can synthesis the desired shape of the transfer function for spectral filtering, such as notches to reject far-out spurs, and high-pass filtering to suppress close-in phase noise. A fully integrated design achieves a measured spur cancellation of 15dB at 250MHz and 750MHz offset as well as phase noise cancellation from 4MHz to 200MHz offset with maximum 25-dB cancellation depth for a 1-GHz clock. The proposed ideas have been verified through a fabricated 65-nm CMOS prototype with power consumption of 11mW from a supply voltage of 1.2V.

Furthermore, we will demonstrate a novel clock multiplier architecture that achieves low jitter and also insensitive to frequency drift without a continuous frequency tracking loop (FTL). With the proposed digital spur calibration techniques, the spurs can be effectively suppressed down to -50.9dBc. Fabricated in 28-nm CMOS technology, this prototype presents an integrated jitter of 138fs_rms while consuming only 6.5mW from a 1-V/0.8-V supplies and achieving -249dB FoM. A detailed study on the mechanisms of jitter performance affected by frequency drift is included, which provides a theoretical justification to the approach. Also, the time domain/frequency domain analysis on digital spur calibration are discussed as well. Finally, an improved version with lower power consumption and generalized multiplication ratio is also realized in a test chip in 28-nm CMOS technology.