With the advent of 2.5D and 3D packaging, there has been increasing interest in chiplet architectures, which provide a cost-effective solution for large-scale systems. Chiplets reduce fabrication cost via yield improvement and also provide an opportunity to conveniently incorporate accelerators to existing systems. Currently, there are existing performance models for the RoCC near-core interface in FireSim, and PCIe is an old standard that is very well explored. However, the latency of chiplet interfaces is between that of the two aforementioned technologies, and is not well studied yet. As such, it has become increasingly important to productively and accurately model performance and latency of chiplet interconnects. Hence, this project aims to support high-performance chiplet connection and system modeling in FireSim, an FPGA-accelerated hardware simulation system, which will enable further studies on both hardware and software systems management for chiplet systems.