Integration of Hf-based ferroelectric materials into the MOSFET gate stack introduces new physics that potentially enables continued scaling for both CMOS and memory devices. The electrostatic potential amplification effect arises when the device is engineered to depolarize and hence stabilize the ferroelectric negative capacitance state, which eliminates the ferroelectric hysteresis and enhances the gate control. On the other hand, when the ferroelectric layer is thick enough to overcome the depolarization field, non-volatile memory function can be realized through the remnant polarization states. Such systems exhibit process and structural compatibility with CMOS technology and thus are of significant application relevance. Experiments have demonstrated low-voltage operations for both types of devices, showing promising prospects for next-generation logic devices with high reliability.

To harness the effects for designing the NCFET and FeFET devices, it is important to understand the behaviours of the ferroelectric layer in the relevant states. In this dissertation, the polarization responses of negative capacitance states are modeled from different aspects through self-consistent device and circuit models that are calibrated to experimental measurements. First, the 101-stage ring oscillator consisting of 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance are used to study the response speed of the negative capacitance effect. The consistency of the device DC characteristics and the circuit oscillations with less than 10ps per-stage delay confirm the fast negative capacitance response. Next, NCFET device characteristics and scaling trends that are unexpected by conventional theory were explained with non-linear negative capacitance responses as described by the Landau's phenomenology. Design insights are drawn, and the observation bodes well for extending the MOSFET gate length scaling limit. Finally, high-speed NCFET RF operations are projected and designed based on experimental characterization results and Monte-Carlo transport simulations. Silicon-channel NCFETs are expected to achieve cutoff frequency over 400GHz with standard SOI device structures and over 650GHz with air-gap spacers.

The carrier dynamics of memory program and readout operations for an n-type SOI FeFET are studied through TCAD simulations. Gate-induced drain leakages during the program operation with large negative gate biases can result in excessive hole concentrations with lifetime exceeding microseconds during the hold phase. While the excess holes result in approximately 100ps delay in the readout phase before a large read margin can be detected, it benefits the program speed and the quasi-steady-state read margin. Therefore, such effects can be utilized for low-power memory applications through proper SOI FeFET designs with the awareness of excess carrier dynamics.