The emergence of the Internet of Things (IoT) has brought energy consumption to the forefront of challenges for future information processing devices. Digital logic integrated circuits (ICs) implemented with complementary metal-oxide-semiconductor (CMOS) transistors have a fundamental lower limit on energy consumption due to their non-zero OFF-state current (IOFF) and finite sub-threshold slope. In contrast, micro-electro-mechanical (MEM) switches (relays) can achieve zero IOFF and have abrupt switching characteristics; therefore, they have attracted growing interest for ultra-low-power computing applications.

This dissertation first addresses challenges for realizing millivolt operation of relay ICs. The impact of electrode configuration on contact resistance and hysteresis voltage is investigated, and it is found that reducing the number of contact dimples from 4 to 2 improves the tradeoff between on-state resistance and minimum operating voltage. With an anti-stiction self-assembled monolayer (SAM) coating, a variety of pass-gate logic circuits using the new 2-contact-dimple relay design are demonstrated to operate with sub-50 mV voltage signals; these include AND, OR and XOR gates and a 2:1 multiplexer (MUX). Multi-functional MEM relay circuits are also demonstrated including a majority gate, 2-bit 2:1 MUX, and dual-polarity gates (XOR/XNOR).

Next, this dissertation addresses remaining practical challenges and discusses opportunities for MEM relay technology. A new method using voltage pulses to reliably break down native oxide on contact-electrode surfaces is developed. SAM coating and operation in liquid dielectric media are explored for improving on-state resistance stability for tungsten contacts in ambient conditions. Finally, MEM relays are demonstrated to function well in extreme environments across a wide temperature range.

Finally, this dissertation proposes a novel relay design that incorporates a beam with negative stiffness to reduce the body bias voltage necessary for millivolt operation. This compensated relay design is investigated with the aid of computer simulations, and is found to provide for improved tradeoff between relay switching energy and turn-on delay under certain conditions. The effects of process-induced variations on relay switching voltage are studied and compared for the compensated relay design vs. a conventional relay design.




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