High-performance power conversions are essential in many applications, especially in the fast-growing computing industries as well as the wireless sensor networks. A common example in mobile devices is the dc-dc converter that converts the energy from a 4 V Li-ion battery to 1 V CPU / GPU chips, where efficiency and form factor are of the most important concerns. Meanwhile, the source voltage increases with the processed power to reduce wire conduction loss, e.g. 48 V DC grid for data centers. In particular, a hybrid approach has shown great potential in achieving high efficiency, high power density, and high conversion ratio, due to its efficient passives and switch utilization compared to the conventional buck and switched capacitor (SC) converters.

In this work, the development of a hybrid or resonant SC (ReSC) converter, along with its soft-charging feature, is illustrated to address the fundamental limits of conventional SC converters and efficiently utilize the high energy density of capacitors. On top of that, various SC topologies are synthesized from a single unit cell for obtaining higher conversion ratios. While several optimization approaches for switch utilizations have been established in recent studies, they mainly focus on the ideal switch model but with the absence of practical considerations. Therefore, a more comprehensive design and comparison framework for commercially available switches and passive components with various voltage domains will be elaborated throughout this work, in conjunction with the analysis and experimental results. The proposed framework serves as a selection guideline for topologies, and it is further solidified through various power converters with optimized switch employment, i.e. an on-chip 4-to-1 V Dickson converter and an on-chip three-level boost converter implemented using the custom switch sizing and voltage rating in 65 nm CMOS process; a 48-to-4 V two-stage ReSC and a 4-to-1 bi-lateral energy resonant converter (BERC) built using ultra-low on-resistance discrete silicon switches.

One of the most critical challenges for all hybrid SC converters is the flying capacitor balancing issues. Any occurrence of imbalance in the flying capacitor voltage leads to increased voltage stress on the switching transistors; meanwhile, the inductor current ripple is increased leading to higher conduction loss. An auto-capacitor-compensation pulse frequency modulation (ACC-PFM) controller for three-level converters is proposed to address it by inherent negative feedback between unbalanced voltage and injected charge. The hybrid approach employed in ACC-PFM, i.e. peak current-mode control with constant-off time and valley current-mode with constant-on time, establishes not only a balanced flying capacitor voltage but also a full-range output voltage regulation.

To further improve the efficiency and power density, two main types of floating supplies, i.e. voltage borrowing technique (employ an existing voltage) and bootstrap circuit (generate a new voltage), are introduced, compared and implemented in different situations. It is found that the capacitance density ratio between the transistor gate capacitance and available capacitors determines which type of floating supplies provides a more area-efficient solution. On the other hand, the gate driving of a power MOSFET is investigated. A segmented gate driver with multiple driving strengths is proposed, which is dedicated to reducing the ringing issue by a low-strength driver and maintaining a low conduction loss by a high-strength gate driver after the ringing-sensitive region. Gate driving techniques including floating supplies and segmented gate drivers are also required by other classes of power converters, particularly when dealing with high voltage using low-voltage devices.

Lastly, passive reduction techniques are developed to further enhance the energy utilization of the passive components, along with the quantitative analysis of multiphase interleaving in hybrid SC converters. A novel BERC concept merges the resonant inductors for the multistage approach, by simultaneously using voltage- and current-type hybrid SC converters. Both passive reduction techniques not only significantly reduce the converter size, but they are also beneficial for high-current applications since lower inductance with higher saturation current can be employed. Therefore, an excellent high power density can be achieved.

Several on-chip and discrete hardware prototypes for hybrid SC converters have been implemented, measured, and showing promising performance in efficiency, power density, and conversion ratios compared to prior arts, which are suitable for applications ranging from point-of-load (PoL), data center power deliveries and energy harvesting. Meanwhile, the hybrid approach offers a lot more design freedom in optimizing the switches and passives utilization, providing more opportunities in further improvement and research topics for high-performance power converters.




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