Silicon-photonics (SiPh) has emerged as a viable solution to handle exponentially growing data traffic in today’s data centers. It transfers data faster and over a distance longer than that possible with traditional electronics, while leveraging efficiency and cost benefits of existing high-volume CMOS manufacturing infrastructure. As the SiPh platforms mature, new high-performance photonics blocks integrated close to CMOS transistors are made available. By moving certain functionality to these optical blocks, the performance of conventional analog mixed-signal circuits can be improved to enable exciting new integrated applications like LiDAR, biosensing, high-performance computing, etc. This thesis demonstrates an optical SiPh link with a reduced laser power requirement and an optically sampled analog-to-digital converter. Both of these systems benefit from the availability of integrated SiPh blocks next to CMOS transistors. The laser power used by a SiPh link can be reduced by improving the optical receiver (Rx) sensitivity and reducing the optical path loss. To improve the Rx sensitivity, a differential detector is monolithically integrated with the low-noise CMOS analog frontend (AFE), while the optical path loss is reduced by adopting a laser-forwarded architecture. The differential detector enables the fully differential operation of AFE to suppress power supply and common-mode noise. Measurement and performance comparison of two variants of differential detector implemented on two test-chips is presented. The proposed microring resonator differential detector enables the receiver to achieve a record OMA sensitivity of -18 dBm at 12 Gb/s. Modeling and characterization of this detector are also covered in this thesis. Further, a coherent laser-forwarded binary-phase-shift-keying (BPSK) link at 10 Gb/s is shown with all the required photonic blocks, like phase modulator, 3-dB coupler, and balanced detectors, fully integrated into a monolithic zero-change 45nm SOI CMOS. This link operates with 3 dB less laser power than state-of-the-art NRZ monolithic SiPh links. Lastly, the performance of conventional CMOS ADCs is often limited by sampling clock-jitter, input sampling bandwidth, and routing of input and clock to the sub-ADCs. To overcome these limitations, this thesis demonstrates an optically sampled ADC that moves the sampling function to the optical domain where ultra low-jitter (<10 fsrms) optical pulses from a mode-locked laser sample an RF input signal with very high sampling bandwidth. An ADC prototype, realized in a 3D integrated silicon-photonic platform, achieves 37 dB SNDR (6b ENOB) for 45GHz input with<36fs estimated sampling jitter. Circuit techniques used for overcoming issues like single-ended to differential conversion and cross-talk are described in detail.




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