Description
Deep scaling of CMOS technology has provided an exceptional opportunity for wideband high data-rate digital communication. However, since the medium between transceivers accept only analog signals, use of analog to digital converters is inevitable. Currently, ADCs are the bottleneck of communication links, where speed trades off with resolution. Moreover, all digital equalization is desirable but necessitates higher resolution and higher bandwidth ADCs. Several methods for increasing the speed of ADCs are considered in this thesis. An extensive analysis, confirmed by simulations, on the jitter-induced error shows that proper system architecture can improve the total SNDR of ADCs.