Among different ADC architectures, the successive approximation register (SAR) ADC has a flexible architecture, high power efficiency and is suitable for the digital CMOS process. Its building blocks rely on MOS switches and latches, which makes it strongly benefits from technology scaling. Time-interleaving (TI) architectures can provide a higher sampling rate because they help relax the power-speed trade-offs of ADCs. Therefore, combining SAR with time-interleaving becomes a good solution to many digital signal processing applications that require power-efficient analog-to-digital conversion. Based on Berkeley Analog Generator (BAG), a time-interleaved SAR ADC generator has been implemented in different technologies. To explore the design flow using circuit generators, this report discusses the working principle and implementation of time-interleaved SAR ADC. A test chip has been taped out in Intel22nm FFL process, containing 6 different versions of ADCs. In each design, a 9-bit 16-way TI-SAR ADC samples at 10GS/s with a memory block storing the digitized result from ADC.