VLSI design in general -- microprocessor design in particular -- has been treated more like an art than a science in the past. The goal of this thesis is to explain the science of VLSI design to someone who wants to build a microprocessor. This can be accomplished by providing a quantitative way to evaluate, and a systematic approach to design, a microprocessor. Resources and complexity are two separate ways a microprocessor designer can pay for performance. The microprocessor designer must evaluate the performance, resources, and complexity tradeoffs quantitatively. In this thesis, the SPUR (SPUR stands for Symbolic Processing Using RISC Machines) CPU microarchitecture is used as example to show how performance, resources, and complexity tradeoffs can be evaluated quantitatively. A systematic approach to microarchitectural design is then developed based on the SPUR CPU design experience. The SPUR CPU is implemented in 1.6um, double layer metal, CMOS technology. It consists of 115,000 transistors, runs at 100ns, and consumes 0.8W of power. Important features of the SPUR CPU are: an internal instruction cache; a four-stage pipeline; support for LISP; a cache controller interface for multiprocessing and virtual memory support; and a parallel coprocessor interface for floating point arithmetic support. All these features make the SPUR CPU significantly different and more complex than previous generations of Berkeley RISC machines.




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