There is a broad spectrum of design styles that have proven successful for the construction of VLSI circuits and systems. Semi-custom to full-custom design styles offer a wide range of resulting performance, expected turn-around time, and required design effort. Implementation alternatives, such as replacing dynamic memory for static memory to implement a denser on-chip memory, also exist at all levels of design hierarchy. To make the best use of scarce resources on a single chip microprocessor and to make the emerging CAD tools truly useful, alternatives in the implementation of a microprocessor must be carefully evaluated. The research reported in this thesis focuses on issues concerning these alternatives, especially in the areas of on-chip memory design and automated control logic design.

The methodologies and techniques used to maximize the performance of a full-custom VLSI microprocessor, called the SPUR CPU, is initially presented to provide an overview of microprocessor design strategies. The rest of the research presented is transpired from new ideas and better alternatives which have become available since the SPUR CPU. These are based on lessons learned in the SPUR design and advanced computer-aided design tools such as multi-level logic synthesis system. A rigorous evaluation of these alternatives is attempted and results from the evaluation establish the effectiveness of the alternatives considered.

To increase the area efficiency of the on-chip memory, two memory design techniques are proposed and evaluated. Selective invalidation instead of refreshing, implemented using low overhead dynamic CMOS circuits, can effectively eliminate the refreshing requirement of dynamic memory. With this scheme, the size of an on-chip local memory can be substantially increased without increasing the scarce silicon area. Trace-driven simulations show the effectiveness of this scheme over a simple invalidation scheme. The demand for high bandwidth local memory expedited by parallel execution of programs through multiple functional units requires a fast, stable, yet compact multi-port memory cell. A single-ended access, static memory cell operated at reduced voltage levels is proven to be useful for such applications.

A part of this research is devoted to investigating various layout styles for microprocessor's control. Recently, various VLSI CAD tools have emerged to facilitate the hard-wired control design. Behavioral synthesis and multi-level logic optimization systems provide particularly efficient and high-performance hard-wired logic implementation, even with semi-custom layout styles, such as standard cell-based design. All new design methods aim for simplicity and regularity. The standard cell based design style, when combined with multi-level logic optimization, can provide a resulting design as good as full-custom version but in much shorter design time.




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