This research effort explores efficient methods for the design synthesis of monolithic CMOS operational amplifiers. A synthesis system has been developed. It, called OPASYN, takes as inputs system level specifications, fabrication-dependent technology parameters, and geometric layout rules. Based on the general domain of the specifications, the program first selects an appropriate circuit topology from a database using heuristic pruning of the decision tree. Optimal values for the set of design parameters of the chosen circuit are then determined so as to meet the design objectives. Analytic models of several widely applicable operational amplifier circuit topologies have been developed to eliminate expensive circuit simulation and sensitivity analysis in the inner loop of the optimization step. Subsequently, design-rule-correct mask geometries are constructed using a macro cell layout style. Primitive circuit elements such as transistors, transistor pairs, and capacitors are produced by parameterized leaf cell generators and assembled according to circuit-dependent slicing trees that guarantee sound arrangements of the individual components. The synthesis process is fast enough for the program to be interactively used at the system design level by system designers who are inexperienced in op amp design.




Download Full History