For future technology nodes, SRAM scaling will require device and circuit innovations to suppress variation. Multi-gate devices and extended spacer lithography processes can be used to reduce random variability at its source. Feedback circuits can be used to reduce systematic SRAM variation after fabrication. Implementation of any one of these techniques is expected to result in a significant yield improvement of several sigma. In combination, these techniques are expected to enable robust SRAM scaling to the end of the roadmap.