SRAM scaling, a major driver of microprocessor development, is threatened by increasing variation in transistor parameters such as threshold voltage and gate length. With a target-based model for device I-V characteristics, the effects of these variations on SRAM performance can be well understood and predicted. A robust, iterative algorithm for estimating SRAM cell yield is developed. The analysis is extended to time-dependent reliability problems, and a statistical methodology for robust cell design is presented.

For future technology nodes, SRAM scaling will require device and circuit innovations to suppress variation. Multi-gate devices and extended spacer lithography processes can be used to reduce random variability at its source. Feedback circuits can be used to reduce systematic SRAM variation after fabrication. Implementation of any one of these techniques is expected to result in a significant yield improvement of several sigma. In combination, these techniques are expected to enable robust SRAM scaling to the end of the roadmap.




Download Full History