The performance of the memory system of VIRAM is studied for various types of image accesses representative of multimedia applications. The performance of VIRAM-1 and other variations on the VIRAM architecture are characterized. The mean bandwidth for loading images of various sizes for the default VIRAM configuration is 6.4 GB/s for a horizontal image access pattern, 0.38 GB/s for a vertical image access pattern, 1.4 GB/s for an 8 x 8 blocked image access pattern, and 0.20 GB/s for a random image access pattern. For stores, the mean bandwidth is 6.4 GB/s, 0.19 GB/s, 1.1 GB/s, and 0.10 GB/s for horizontal, vertical, 8 x 8 blocked, and random image access patterns, respectively. These compare to peak bandwidths of 6.4 GB/s, 0.8 GB/s, 6.4 GB/s, and 0.8 GB/s for the horizontal, vertical, 8 x 8 blocked, and random image access patterns, respectively.

Averages can be deceiving, however, as there is sometimes a wide variance amongst the results. This phenomena is especially true for strided accesses, found in the vertical image access pattern, whose performance is highly dependent on the stride. Hardware-based data layout alternatives are examined for their effect on strided memory performance. An alternative layout modestly improves the mean performance of the vertical access pattern, but it increases the variance and decreases the performance of some particular cases. A simple address hashing scheme decreases the variance and increases the performance of some particular cases, but it decreases the mean performance of the vertical access pattern.

The bottlenecks to performance within the memory system are sometimes bank conflicts, sometimes sub-bank conflicts, and sometimes a mixture of the two. When sub-bank conflicts are a significant factor, the performance significantly increases if each bank within the DRAM is divided into sub-banks, and load bandwidth is higher than store bandwidth due to the additional sub-bank busy time for stores. Other factors limiting the performance of the VIRAM memory system include short vectors, insufficient issue bandwidth, and the effects of a simplified pipeline control. Loop unrolling is necessary for maximizing performance when there is insufficient issue bandwidth to keep one or both memory units busy, in the horizontal and blocked image access patterns. Data alignment is only significant on unit stride accesses when there is sufficient issue bandwidth to keep the vector memory unit(s) busy.

The memory system is a limiting factor in the ability of the vector unit to effective scale both the number of lanes and the number of address generators. Scaling improves as the number of sub-banks increases for cases in which sub-bank conflicts are a significant factor.

Even though there are limitations to scaling and all but the unit stride accesses of the horizontal image access pattern achieve less than the peak performance, the absolute performance of VIRAM-1 is impressive compared to conventional, cache-based machines. For comparison, the measured unit stride performance of a memory to memory copy on a PC running at twice the clock frequency of VIRAM-1 is only 304.0 MB/s, a small fraction of the sustainable unit stride bandwidth of VIRAM-1.




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