To cope with the increasing complexity of electronic systems and time-to-market requirements, platform-based design (PBD) was proposed as a powerful design methodology. The core concepts in PBD are (1) the separation of concerns between functionality and architecture, which facilitates design reuse at all design levels, and (2) the successive refinement of the design by mapping functionality onto architecture. Optimal mapping optimizes a set of objective functions while satisfying constraints on the mapped design. Formalized design methods gain traction in the designer community when they facilitate automating the design process from specification to implementation, as witnessed by the RTL to layout ASIC flow. While logic synthesis and layout synthesis, which can be seen as special cases of optimized mapping, have been widely researched and many excellent algorithms have been made available, the mapping problem at the system level is typically solved in an ad-hoc and implicit manner based on designer experience.
This dissertation proposes a formal mapping procedure that enables the development of automatic tools. The mapping procedure is based on a two-stage process. First a common semantics between function and architecture models is determined and an appropriate set of primitives is selected to decide the abstraction level. Then mapping is formulated and solved as an optimal covering problem where the function model is covered by a minimum cost set of architecture components.
We demonstrate the use of the formal approach for the optimal mapping problems in two widely different application domains which feature different models of computation for representation as well as different implementation platforms. This process is general in the sense that it can be applied at all levels of abstraction and for a variety of system level design problems.
In our case studies, Metropolis -- a design framework for platform-based design -- was used to validate our approach. And the insights gained from these case studies motivated the development of Metro II, the next-generation of Metropolis.
Title
Optimizing Mapping in System Level Design
Published
2008-09-26
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
EECS-2008-126
Type
Text
Extent
161 p
Archive
The Engineering Library
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