The second part of the paper describes the memory management unit and cache controller (MMU/CC) chip. System level design issues such as multiprocessor cache coherency and synchronization among chip sets are also considered in the second part. Both chips are implemented in a 1.6 um double-layer-metal CMOS technology, and are being used in a multiprocessor workstation (SPUR) successfully executing its own operating system called Sprite as well as many applications including LISP programs.
Part I title: A RISC Microprocessor with Coprocessor Interface and Support for Symbolic Testing
Part II title: A Memory Management Unit and Cache Controller