It is becoming increasingly popular to describe real time signal proessing systems targetted for FPGA or ASIC implementation using structural signal flow graphs. We have implemented support for generation of synthesizeable as well as testbench VHDL code from Ptolemy II models. A helper based approach borrowing heavily from the existing Ptolemy II C code generation framework is used. This work demonstrates the extensibility of the helper based code- generation approach and sets the stage for future research in synthesis of efficient hardware descriptions from heterogenous visual models.
Title
VHDL Code Generation in the Ptolemy II Environment
Published
2008-10-28
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
EECS-2008-140
Type
Text
Extent
9 p
Archive
The Engineering Library
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