I have built a compiler that generates code for a family of application-specific digital signal processors developed at Berkeley by members of the Lager project. Application-specific processors are programmable processors that serve as components of application-specific integrated circuits.

The compiler accepts a C-like language and generates code using a machine description provided by the user. My work has demonstrated the utility of a user-retargetable compiler in selecting an appropriate processor architecture for a given program. The designer begins with some preexisting architecture, compiles the program, and then evaluates changes to the architecture by recompiling the program with a modified machine description and observing the effect on the instruction count. I describe two cases in which this approach has been used at Berkeley to develop signal-processing chips.

The compiler's target processors have irregular datapaths like those of typical off-the-shelf signal processors, but execute open horizontal microcode (i.e., the machine instructions are vectors of control signals with little restrictive encoding). The usual technique for generating horizontal microcode is to first generate vertical code and then compact this in a separate pass. This approach is inappropriate for datapaths such as ours, for which I have developed an effective, new technique. It generates and schedules code in a single pass over a straight-line program segment, doing local register allocation and chaining of operations on the fly, using a network-flow algorithm to enforce the constraints that are needed, in this approach, to avoid blocking. I demonstrate the effectiveness of the technique by comparing compiler-generated and hand-written code for several signal-processing programs.




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