This thesis develops estimation and control techniques in power converters. The target applications are voltage regulators for modern microprocessors (VRM) and distributed DC power systems (DPS).

A method for the on-line calibration of a circuit board trace resistance at the output of a buck converter is described. This method is applied to obtain an accurate and high-bandwidth measurement of the load current in the VRM applications, thus enabling an accurate DC load-line regulation as well as a fast transient response. Experimental results show an accuracy well within the tolerance band of this application, and exceeding all other popular methods.

A method for estimating the phase current unbalance in a multi-phase buck converter is presented. The method uses the information contained in the voltage drop at the input capacitor's ESR to estimate the average current in each phase. The method can be implemented with a low-rate down-sampling A/D converter and is not computationally intensive. Experimental results are presented, showing good agreement between the estimates and the measured values.

An online adaptation method of the gain of an output current feedforward path in VRM applications is developed. The feedforward path can improve substantially the converter's response to load transients but it depends on parameters of the power train that are not known with precision. By analyzing the error voltage and finding its correlation with the parameter error, a gradient algorithm is derived that makes the latter vanish. Experimental results show a substantial improvement of the transient response to a load current step in a prototype VRM.

Impedance interactions between interconnected power subsystems are analyzed. Typical examples of these interconnections are a power converter with a dynamic load, a power converter with an input line filter, power converters connected in parallel or cascade, and combinations of the above. A survey of the most relevant results in this area is presented together with detailed examples. Fundamental limits on the performance of the interconnected systems are exposed and a system-level design approach is proposed and corroborated with simulations.




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