Rapid adoption of multiple cores in computers has been a driving force to empower computing. The challenge with multiple cores is to transfer large amount of data efficiently between processors and memories. Network-on-chip (NoC) is been looked upon as a potential solution to transfer the data efficiently. This paper presents the design space exploration of one of the most important components of NoC – Router. A working prototype of the router designed by Daniel Becker was scaled to increase the number of ports to 16, 32, and 64 and their area, power, and timing numbers have been reported. The analysis is done on Synopsys tool flow. Crossbar is identified as one of the bottlenecks of the original prototype and a recommendation of the improved crossbar is also presented. The improved crossbar resulted in 33% reduction in area and reduces the tools run time from 36+ hours down to ~15hrs for a 64 port router.
Title
Petabit Switch Fabric Design
Published
2015-05-14
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
EECS-2015-91
Type
Text
Extent
46 p
Archive
The Engineering Library
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