The power consumed by digital integrated circuits has grown with increasing transistor density and system complexity. One of the particularly power-hungry design features is the generation, distribution, and utilization of one or more synchronization signals (clocks). In many state-of-the-art designs, up to 30%-50% of the total power is dissipated in the clock distribution network.

In this work, we examine the application of sequential logic synthesis techniques to reduce the dynamic power consumption of the clocks. These optimizations are sequential because they alter the structural location, functionality, and/or timing of the synchronization elements (registers) in a circuit netlist. A secondary focus is on developing algorithms that scale well to large industrial designs.

The first part of the work deals with the use of retiming to minimize the number of registers and therefore the capacitive load on the clock network. We introduce a new formulation of the problem and then show how it can be extended to include necessary constraints on the worst-case timing and initializability of the resulting netlist. It is then demonstrated how retiming can be combined with the orthogonal technique of intentional clock skewing to minimize the combined capacitive load under a timing constraint.

The second part introduces a new technique for inserting clock gating logic, whereby a clock's propagation is conditionally blocked for subsets of the registers in the design that are not actively switching logic state. The conditions under which the clock is disabled are detected through the use of random simulation and Boolean satisfiability checking. This process is quite scalable and also offers the potential for additional logic simplification.