The current trend in the computing industry is to offer more performance by leveraging more processing cores. In light of continuous increase of microprocessor cores, there is a growing need for efficient on-chip interconnect. In this project we explored the designing of high radix routers which is the basic building block for interconnect networks. As the number of ports in the router increases its complexity increases. We analyzed the bottlenecks of the design and worked on the improvement of it. We investigated all the major sub-blocks of the router. We implemented new arbitration schemes which improved performance over conventional arbiters. We have also implemented SRAMs as buffers which helped in reducing area of the router. In high radix router, routing of signals increases exponentially which dramatically increases tool run time, hence we worked on exploring design tool configurations and hierarchical designing. Also various crossbar architectures has been implemented and studied, which are major bottleneck for routing congestion. Finally, we concluded the appropriate schemes for the implementation of all the design blocks in the router.