Our project, Next Generation Memory Interfaces, aims to develop a physical interface for the latest memory standard, DDR4 SDRAM (Double Data Rate 4th generation, Synchronous Dynamic Random Access Memory). This report focuses on timing block of physical interface. The relationship between Clock signal and Data signal is important in high speed systems. The data is only sampled at the edges of Clock signal. In order to capture the data correctly, the Clock signal must be well aligned with Data signal. In DDR4, the Delay Locked Loop (DLL) is used to fix the timing variations caused by process, voltage, and temperature (PVT). The delay line is one of the most important parts of DLL. It consists of a group of delay cells. This report introduces the design of the delay line using Cadence Virtuoso.