The DDR4 standard allows for memory to be accessed at twice the data rate of its preceding standard, DDR3 while simultaneously reducing the total power consumption and increasing the memory density. In this project a physical layer (PHY) interface for the DDR4 subsystem has been conceptualized, and designed. As memory devices eternally seek to be faster, denser and extremely low power consuming systems, the PHY interface will get us another step further in this quest. In this report, the challenges and circuit techniques associated with the design of this high data-rate interface have been discussed along with the main differentiating factors between DDR4 and its predecessor, DDR3. The design process and results for the receiver front-end of the physical layer are among the major focus points of this report.