In this work, we address the problem of rising variability and insufficient variability modeling in two ways. Firstly, by characterizing variability in a deeply-scaled technology node, and secondly by developing a methodology for simple, fast model tuning for design-specific yield optimization.
Technology characterization is achieved by designing a set of dedicated test structures in a 28nm FDSOI technology. Test structures include both device characterization as well as high-speed comparator characterization, and focus on design-dependent, layout-dependent and topology-dependent sources of variation. Worst-case measured within-die device variation goes up to 11% while a 46% of current variation is measured across different dies. Layout-dependent systematic effects do appear to be significant in this technology. Several comparator topologies are also measured, showing a direct link between comparator sensitivity and measured offset.
Yield optimization is achieved by model customization to a specific design. A methodology that uses backward propagation of variance and sparse regression techniques is developed in order to achieve this. The methodology is shown to have the ability to tune models to variability structure measurements, decreasing the estimated prediction error from 30% to <4%.