A voltage-island architecture for systems-on-chip is an effective way to reduce active and static power. For such multiple supply designs, various layout architectures exist; however, placement algorithms that take advantage of a circuit rows style of implementation are not available to designers today. This paper presents two algorithms to place standard cells in a circuit rows style of implementation for dual-supply digital designs using double-height level converting flip-flops. Our results show significant improvement in terms of wirelength over a simple bi-partitioning scheme that is currently employed in manufactured designs. On average, we show a 21% wiring overhead for multiple-supply design using our new techniques compared to an 81% overhead under the bi-partitioning scheme. This paper represents a first work quantifying the physical design overhead of a dual-supply system in the context of multiple-supply aware placement algorithms.
Title
A Placement Technique for Multiple-Voltage Design
Published
2006-10-19
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
EECS-2006-133
Type
Text
Extent
10 p
Archive
The Engineering Library
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