ATV, the Abstract Timing Verifier, is a program to perform static timing analysis of dependency graphs derived from logic designs, analyzing worst-case paths using an abstract representation of time and delays that enables a user to choose different representations of time and delays for the analysis.
This technical report describes how to use ATV to analyze designs, including clock phrase length analysis of designs that include transparent latches. Background information on the principles behind ATV, including descriptions of several models not yet implemented in ATV, is presented in the main body of my dissertation, available as the companion technical report, Abstract Timing Verification for Synchronous Digital Systems.
Title
User's Guide to ATV, an Abstract Timing Verifier
Published
1988-06-01
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
CSD-88-426
Type
Text
Extent
98 p
Archive
The Engineering Library
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