A central problem in building large scale parallel machines is the design of the interconnection network. Interconnection network design is largely constrained by packaging technology. We start with a generic set of packaging restrictions and evaluate different network organizations under a random traffic model. Our results indicate that customizing the network topology to the packaging constraints is useful. Some of the general principles that arise out of this study are: 1) Making the networks denser at the lower levels of the packaging hierarchy has a significant positive impact on global communication performance, 2) It is better to organize a fixed amount of communication bandwidth as a smaller number of high bandwidth channels, 3) For shared memory based communication primitives it is better to make the number of memory modules smaller than the number of processors and 4) Providing the processors with the ability to tolerate latencies (by using multithreading) is very useful in improving performance.
Title
Customizing Interconnection Networks to Suit Packaging Hierarchies
Published
1991-10-31
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
CSD-93-725
Type
Text
Extent
28 p
Archive
The Engineering Library
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