Recent advances in low power radio design have enabled a broad range of low activity applications such as smart utilities, health monitoring, building and industry automation, automotive control and monitoring, wireless control and etc. The key challenge to implement these applications is to reduce the average power consumption spent on wireless communications. A traditional way to solve this is to implement protocol based duty cycling which leads to a tradeoff between reduced average power consumption and increased system latency. A smarter solution is to use a dedicated wake-up receiver continuously monitoring the channel and activating the main receiver upon detection of a wake-up signal. The use of a wake-up receiver helps to improve the overall power performance while keeping the system latency bounded.

This dissertation addresses challenges and concerns of designing an ultra-low power high performance wake-up radio. It proposes a two-step wake-up architecture including energy detection mode and address detection mode to reduce the active power dissipation meanwhile improving the robustness and reliability of the system. Design metrics has been provided to serve as a guideline for detailed circuit implementations. Based on that, a wake-up radio prototype has been built in TSMC 65nm standard CMOS targeting 915MHz band for IEEE 802.15.4g. This prototype focuses on improving the sensitivity performance at an ultra-low power level. It consumes only 45µW in energy detection mode. With 20µs detection time, it is able to achieve a sensitivity of -90dBm at 10-2 error rates. In address detection mode, it consumes 300 µW and is able to achieve a sensitivity of -74.5dBm at 10-3 BER.




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