The goal of this project was to define and demonstrate a subset of the VHDL language [IEEE87] which is consistent with the simulation semantics and yet has an interpretation as a specification. The subset shown in this work incorporates as much of the language as is possible without compromising its interpretation as a specification of system behavior. There is no other subset of the VHDL language which can incorporate more of the semantics of the language, yet retain an interpretation as a specification. To show why this is the largest subset of the VHDL language which has this property, a review of some of the full VHDL language as a specification within this context is problematic at best. A definition of what it means to interpret an executable description as a specification is given in the form of an example of an existing class of languages, the reactive languages, which have this property: being executable yet having an interpretation as a specif- ication. The question then is whether there is a useful subset of the VHDL language that can be shown to be reactive. In fact, within the wide range of uses of VHDL, there is a class of uses that can be interpreted as a reactive specification. The identification of this class of uses, and the restrictions on the language structure that accompany it form the basis of the subset definition. Reactive systems, or equivalently synchronous systems, have the property \ that they respond to events from the environment in which they reside; nothing of interest outside these events and their responses occurs in these systems. The formulation of the definition of reactive systems in terms of events allows for a succinct description of their behaviors as regular expressions. Hence the implementation of a reactive system is naturally in terms of one of the many finite automata which recognizes the regular language that defines the system's behavior. The goal of the subset definition then is to identify the reactive portion of the VHDL language, independent of its language structures, so that the behavior of programs written in the subset may be interpreted as regular expressions, and implemented in terms of communicating finite automata. The Synchronous VHDL subset presented here is derived through a restriction on the abstract simulator that defines the meaning of a VHDL program. The focus here is on restricting the simulator behavior and using that restriction to drive the definition of the VHDL subset, instead of the other way around as has been traditional in the definition of other VHDL language subsets. The result of this work is a description of the subset of the VHDL language that uses only finite-automata-like behavior; it thus has well-defined implementation as a network of communicating finite state machines. In addition to the definition of Synchronous VHDL, a goal of this project was to demonstrate the subset in use. Thus, a major portion of this project was the implementation of a compiler front-end which is used to analyze VHDL source text, converting from the syntax of the language into a form suitable for compilation into a reactive language.