Description
This project presents design and simulation results for a low noise receiver frontend subsystem, which consists of LNA, IQ Mixer, buffer for LO signal, and IF VGA. The cascaded blocks have input return loss of < -15 dB, overall noise figure (NF) of < 5 dB, overall input-referred third-order intercept point (IIP3) of > -26 dBm and input-referred second-order intercept point (IIP2) of > 10 dBm.
Practical biasing circuits are used in blocks simulation to consider performance impairments due to their non-idealities, such as noise. The only ideal source used in simulations is the VDD supply rail. A commercial FD-SOI 28nm CMOS process by STMicroelectronics foundry is used throughout the project.