Historically, the steady miniaturization of the conventional (planar bulk) MOSFET by simply scaling the device dimensions with minimal changes to the conventional transistor design and CMOS process flow has been effective to provide for continual improvements in integrated circuit performance and cost per function with every technology node. However, transistor scaling has become increasingly difficult in the sub-100 nm regime. Increased leakage current and variability in transistor performance are the major challenges for continued scaling of bulk-Si CMOS technology. The benefit of using a spacer gate lithography process to mitigate the effect of gate line edge roughness (LER) is assessed using statistical 3-D device simulations. The simulation results indicate that spacer gate lithography is a scalable technology which can dramatically reduce LER-induced variation in transistor performance. A tri-gate bulk MOSFET design combining retrograde channel doping with a multi-gate structure is proposed to provide an evolutionary pathway for bulk CMOS scaling. The scalability, design optimization, and the effect of systematic and random variations on transistor performance are investigated. As compared with the classic planar MOSFET design, the tri-gate bulk MOSFET provides for superior electrostatic integrity and reduced variability. As compared with SOI FinFET design, the tri-gate bulk MOSFET design is more scalable and less sensitive to device design parameters. As compared with the bulk FinFET design, the tri-gate bulk MOSFET offers comparable performance and variability. Its low-aspect-ratio channel structure is favorable for ease of manufacturing. Thus, the tri-gate bulk MOSFET is a promising structure for CMOS scaling to the end of the technology roadmap. The fabrication process flow and the most critical processes for tri-gate bulk MOSFET fabrication are discussed. Initial device results show that tri-gate bulk MOSFET design is beneficial for reduced variability.