In the last couple decades, the phenomenal growth of mobile electronics is fueling the demand for multi-functional, high performance and ultra-low power integrated circuits. Reduction in Vdd to achieve orders of magnitude reduction of energy consumption is crucial if the promise of many more decades of growth of electronics usage is to be realized. For MOSFETs, Vdd reduction can only be achieved at the expense of speed loss and/or off-state leakage increase because the subthreshold slope is fundamentally limited to 60mV/decade. New transistors with sub-60mV/dec swing allowing Vdd scaling to 0.3V and below are therefore highly desirable. In this research, two approaches to achieve transistors with sub-60mV/dec swing are explored. Feedback FET (FBFET) uses positive feedback to induce an abrupt change in current with a small change in the gate voltage. Experimental results show FBFET can achieve less than 2mV/dec swing, with Ion/Ioff ratio larger than six-orders-of-magnitude. Simulation is used to illustrate the operating principle, and to evaluate the potential of FBFET. Another approach is to integrate negative capacitance element onto the gate stack of MOSFETs. The negative capacitance does not change the transport physics, but rather seeks to "amplify" the gate voltage electrostatically to achieve less than 60mV/dec swing. Design considerations and optimizations of Negative Capacitance FET (NCFET) are explored using simulations. Simulation shows the possibility of achieving hysteresis free, sub-30mV/dec operation of NCFET based on an UTBSOI design. The experimental NCFET result of epitaxial ferroelectric thin film on SOI substrate is presented.




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