A low noise direct-conversion receiver front-end has been designed in a commercial foundry 65nm CMOS process. Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. The image problem has been eliminated in DCR since the intermediate frequency (IF) is zero and the image to the desired channel is the channel itself, therefore, no image reject filter is required at the front-end and the channel selection filter becomes a low-pass filter, which makes on-chip system integration easier. However, DCR suffers from several drawbacks such as performance degradation due to DC offsets, LO self-mixing, 1/f noise, even-order distortion and I/Q mismatch. A DCR front-end consists of RF band-select filter, low-noise amplifier (LNA), I/Q mixer, variable gain amplifier (VGA), low-pass filter (LPF), and an analog-to-digital converter (ADC). Main components such as LNA, I/Q mixer, and VGA have been designed and simulated with power consumption of < 2mW, programmable gain from 20dB to 80dB, input return loss of < -20 dB, overall noise figure (NF) of < 5 dB integrated from bandwidth of 1kHz to 5MHz, overall input-referred third-order intercept point (IIP3) of > -20dBm and input-referred second-order intercept point (IIP2) of > 10 dBm.




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