This work emphasizes this point by exploring a particular application of conductive materials of interest to the electronics industry at-large: packaging interconnects. Without high-performing, robust interconnects, packaged electronic devices and circuits may both suffer from degraded performance due to sub-par electrical performance and fail well before their expected lifetime. Therefore, the development of improved materials and processes for the purpose of fabricating electrical interconnects is of interest to all corners of the electronics community. Unfortunately, in order to fabricate these structures with printed materials and processes, the printed electronics community must first overcome a number of barriers, most of which are discussed in this work.
First, the development of stable jetting conditions for inks containing metal nanoparticles is discussed. A general yet powerful approach to the formulation of rudimentary inks is developed. In tandem with developing strategies for creating reliable inks with respect to jetting, both the solubility enhancement and bound ligand minimization of metal nanoparticles are explored in order to ultimately boost the performance of printed conductors. Using a heuristic-driven experimental approach, metal nanoparticles with very high solubility (nearly 40% by mass) and relatively low ligand content are achieved.
Next, two applications of three-dimensional printing of metal nanoparticle inks are explored. The first is the fabrication of freestanding pillars with the intention of replacing existing solder bump materials and processes. The process parameters most important to this technique, jetting frequency and substrate temperature, are thoroughly explored using both commercially-available as well as custom-made metal nanoparticle inks. In addition, characterization methods including electrical, mechanical, and chemical techniques are applied in order to investigate the sintering process for these three-dimensional features. Ultimately, the electrical and mechanical performance of freestanding pillars are shown to outcompete existing solder bump structures at process conditions that do not exceed 200 °C.
The second application explored is the development of a single-step filling and bumping process for through-silicon vias (TSVs). Using the process developed for freestanding pillars as a foundation, fully-filled TSV processes are developed and studied in detail. The effects of process parameters such as jetting frequency and substrate temperature are investigated. Finally, arrays of successfully filled and bumped TSVs are finally bonded using thermocompression flip-chip bonding and electrically and mechanically characterized. The results indicate that, indeed, printed TSVs provide robust electrical and mechanical interfaces for electronic applications.