Using hardware generators to produce components for modern SoCs enables rapid design space exploration. Embedding these hardware generators in a high-level programming language allows for simpler code, more expressive generators, and correspondingly better quality of results. This thesis describes the use of Chisel (Constructing Hardware in a Scala Embedded Language) to construct an FFT generator. The parametrized generator demonstrates automatic parameter-dependent test generation and seamless system integration. An analysis of FFT scheduling is performed to show how various mathematical properties of the Cooley-Tukey FFT decomposition may be exploited to simplify needed hardware while assuring conflict-free bank accesses for every operation. The resulting circuit throughput, energy, and area are shown to be better than or on par with other FFT generators.
Title
Flexible FFT Optimization and RTL Generation in the Chisel Hardware Design Language
Published
2015-12-18
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
EECS-2015-256
Type
Text
Extent
148 p
Archive
The Engineering Library
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