The trend, as technology advances, is for VLSI implementations of computer systems to use increasingly wider busses and faster clock rates. This report illustrates how the trend affects integrated circuit design in the areas of power and ground design, and output pads. The first section of the report discusses the circuit design issues of inductance effects, CMOS noise margins, clean and dirty supply lines, pad loading and delay, process variation effects, and pad driver design approaches. The second section is an in depth description of the technique used and results obtained for inductance characterization of pin grid arrays. Following that is a section discussing design issues for input and output pad cells, along with a description of the pad cells developed for the Berkeley SPUR project.