A method for optimizing the equalizer architecture under power and bit-error rate (BER) constraints has been developed. This method has been used to optimize the number of equalizer taps and the distribution of signal processing between analog and digital domains. Two chips were built to demonstrate the methodology based on the IEEE wireless personal area network (WPAN) standard.
The first, fully-digital chip implements a single-carrier demodulator that minimizes the power consumption using a parallelized distributed arithmetic architecture. A 2mm x 2mm test chip in a 65 nm CMOS process implements a 6-tap feedforward and 32-tap feedback equalizer for binary phase-shift keying (BPSK) that can be configured to cancel the response of up to 72 symbols while consuming 5.6mW at 2 Gb/s throughput.
The second 1.86mm x 1.86mm chip implements a reconfigurable 4-bit ADC and 6-tap analog equalizer in addition to the digital equalizer for quadrature phase-shift keying (QPSK) demodulation. The analog preprocessor is measured to consume 1.3mW for the driver and 300 uW/tap for the analog equalization. The ADC power consumption varies from 1.2mW to 3.8mW depending on the resolution at 1.76 Gs/s. It is shown that, given a BER requirement, the mixed-signal reconfigurable receiver architecture can reduce the total link power consumption compared to a full-digital fixed transceiver depending on the propagation condition.