Big RISC (BRISC) is a high-speed CPU designed with 100K ECL logic and based on the RISC I architecture. Design, performance, and cost of BRISC is presented. Performance is shown to be better than high end mainframes such as the IBM 3081 and Amdahl 470V/8 on integer benchmarks written in C, Pascal and LISP. The cost, conservatively estimated to be $132,400 is about the same as a high end minicomputer such as the VAX-11/780. BRISC has a CPU cycle time of 46 ns, providing a RISC I instruction execution rate of greater than 15 MIPs. BRISC is designed with a Structured Computer Aided Logic Design System (SCALD) by Valid Logic Systems. An evaluation of the utility of SCALD for computer design is also included.
Title
A Big RISC
Published
1983-07-18
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
CSD-83-143
Type
Text
Extent
89 p
Archive
The Engineering Library
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