This report presents details of the third six-inch baseline run, CMOS170, where a moderately complex 0.35 mu-m twin-well, silicided process was used. This process was based on the first six-inch 0.35 mu-m run, CMOS161. Different research circuits (IC/MEMS) were placed in the drop-in area, i.e. ring oscillators, a MEMS design, a hyperacuity chip and several different memory circuits. A more complex (triple metal) process flow consisting of 66 steps was introduced by this version of the 0.35 mu-m process, with the main objective of matching N-channel and P-channel threshold voltages (Vt, absolute values). According to simulations the NMOS threshold voltage was matched to the PMOS values by decreasing the NMOS Vt implantation dose.
Title
0.35 mu-m CMOS Process on Six-inch Wafers, Baseline Report V
Published
2007-02-09
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
EECS-2007-26
Type
Text
Extent
65 p
Archive
The Engineering Library
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