Field programmable logic devices (FPLDs) are fast emerging as viable alternatives to mask programmed parts because of their rapid time-to-market and low costs. Their application has, however, been limited to implementing random logic, with non-critical timing specifications. This work attempts to advance FPLD usage to high-performance applications as well. A two-pronged approach is adopted. In the first part, CAD algorithms aimed at improving routability and performance of designs mapped to existing look-up table (LUT) based field programmable gate arrays (FPGAs) are developed. The concept of a two-input LUT primitive cell is introduced. This reduces the number of library patterns that require to be stored for an LUT library, and makes it feasible to extend performance-driven library based technology mapping techniques to LUT FPGAs. The performance- driven mapping algorithm accounts for interconnect delay and provides area-delay trade offs. Experiments on benchmark designs show the effectiveness of the new algorithms. In the second part, a new FPLD architecture is introduced. The architecture is based on the concept of time-sharing of logic and routing resources in an effort to have a fully routable, CAD friendly FPLD with predictable timing performance and efficient silicon usage. Real-time reconfiguration of logic and routing resources implements a given circuit in a folded pipe-line fashion, pipe lining at the gate level. Several possible variations of the basic architecture are discussed. A simple synthesis scheme is developed and experimental results are reported. Area and timing analyses demonstrates advantages over existing FPGAs.




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