In the exa-scale age of big data, file size reduction via compression is ever more important. This work explores the possibility of using dedicated hardware to accelerate the same general-purpose compression algorithm normally run at the warehouse-scale computer level. A working prototype of the compression accelerator is designed and programmed, then simulated to asses its speed and compression performance. Simulation results show that the hardware accelerator is capable of compressing data up to 100 times faster than software, at the cost of a slightly decreased compression ratio. The prototype also leaves room for future performance improvements, which could improve the accelerator to eliminate this slightly decreased compression ratio.
Title
A Hardware Implementation of the Snappy Compression Algorithm
Published
2019-05-18
Full Collection Name
Electrical Engineering & Computer Sciences Technical Reports
Other Identifiers
EECS-2019-85
Type
Text
Extent
38 p
Archive
The Engineering Library
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