New design methodologies that quickly and systematically explore power-performance tradeoffs between architectures and design variables at each level of design abstraction can enable design innovation and reduce design cost and design time. This dissertation proposes a novel digital design methodology that systematically evaluates power-performance tradeoffs at each level of design hierarchy in the context of constraints from lower levels of design abstraction. It is a holistic approach that uses sensitivity information, which allows designers to systematically and rapidly traverse a vast design tradeoff space, leading to power-performance optimal architectures and enabling short design times. Little formalism has been built around some of the earlier published works that have proposed sensitivity-based design methodologies. This dissertation formalizes the methodology in an optimization framework and algorithm. The framework is conceived using a previously published custom circuit optimizer for power-performance optimization at the leaf cell. The viability of using physical circuit parameters to estimate sensitivity is investigated and shown to be instrumental in reducing design time required to uncover power-performance optimal architectures. A linear relationship between Cgate/Cwire and sensitivity to gate sizing is uncovered. This first-order linear estimator mitigates the need to calculate derivatives or run large circuit simulations. The use of composition rules is investigated to enable fast generation of energy-delay curves for larger circuit blocks comprised of smaller leaf cells. Energy-efficiency curves are generated for multiple architectures within short periods of time, allowing rapid evaluation of architectures in the context of lower level design constraints and tuning variables such as circuit sizing. The composition process is formalized into an algorithm that can be implemented as a convex optimization program. This provides an automated mechanism for fast design space exploration at architecture, micro-architecture and circuit levels. A digital FIR kernel for use in multi-mode, multi-standard radio transceiver is optimized using the design methodology.




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