Description
Increased memory capacity and processing power in mobile devices has created a need for radios that can transmit data at multi-Gb/s rates over a short range. However, battery capacity has not kept pace with these advances so power consumption must be kept to a minimum to maintain long battery life. Furthermore, consumer devices require low cost components due to the strong market pressures continuously driving down Average Selling Prices (ASP) leading to diminishing margins. This means a fully integrated solution including RF and baseband components is more attractive than a modular solution.
The allocation of 7GHz of unlicensed bandwidth in the 60GHz band and the increasing speed of CMOS technology provides an excellent opportunity for low cost, high data rate, fully integrated radios to fulfill the unique requirements of modern mobile devices. Phased array transceivers using simple modulation schemes should be used due to their high energy efficiency. Phased arrays use spatial power combining to help overcome the high path loss at 60GHz and also provide beam-steering capabilities which can help to overcome fading issues and create a secure means of communication.
Significant progress has been been made recently in the design of mm-wave CMOS building blocks and transceivers, including some phased array transceivers. However, very little attention has been paid to systematic optimization and design of the LO generation and distribution subsystem. In this thesis we use the baseband phase shifting architecture as a vehicle for optimizing LO generation and distribution in phased array transceivers. We propose strategies for optimal low power design with a focus on holistic optimization from architectural choices down to block level design resulting in an optimal and scalable LO distribution methodology. Finally, we present sample designs of building blocks such as oscillators and phase locked loops as well as a full LO generation and distribution subsystem for a 4-element baseband phased-array transceiver in a standard digital 65nm CMOS process.