This report describes the cache memory system of the Aquarius IIU node along with the address translation unit, and the VME interface. The Aquarius IIU node is designed for the parallel execution of Prolog. It is based on the VLSI-PLM Chip that runs the Warren Abstract Machine Instruction Set (an intermediate language for Prolog). We have connected many of these nodes using a shared bus to form a multi, which has its own shared memory and snooping caches and is used as a backend Prolog engine to the host (SUN3/160). On every node, there are two controllers for data and instruction cache that cooperate to support Berkeley's snooping cache-lock state protocol, which minimizes bus traffic associated with locking blocks. The nodes share memory using the VME bus; the page faults and memory management are handled by the host. The components of the Aquarius IIU node have been simulated at the gate level.
Details
Title
The Aquarius IIU Node: The Caches, the Address Translation Unit, and the VME bus Interface
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