This Capstone project aims to develop a novel memory controller to deliver a high-bandwidth interface for the DDR4 memory standard. DDR4 is the current cutting edge memory standard developed by JEDEC. The high-bandwidth interface is used as a communication link between a memory controller operating at 400MHz and a DDR4 SDRAM. Our team developed a physical interface that can transmit 3.2Gbps of data using only one transmission line. The design consisted of five major sub-modules: 8 to 1 Serializer, Transmitter, Receiver, 2 to 8 Deserializer, and Clock-Generating circuits. This paper discusses the design process, as well as the final results, of the completed 3.2Gbps 2 to 8 Deserializer module. The Deserializer discussed in this paper takes two data-line inputs operating at 1.6Gbps each, and deserializes them onto eight data-lines operating at 400Mbps each.