FinFET technology already has been adopted by the semiconductor industry beginning at the 22 nm node of complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) technology, due to the superior electrostatic integrity of multi-gate transistor structures. Although silicon on-insulator (SOI) wafers are ideal substrates for the manufacture of FinFETs with low off-state leakage current, they are more expensive than conventional bulk-silicon wafers. If a bulk-silicon wafer is used as the substrate for FinFET fabrication, heavy "punch-through stopper" doping is needed at the base of the fins to suppress off-state leakage current. A conventional doping process results in dopants within the fin (channel region), however, which degrades transistor on-state performance. The benefits of a super-steep retrograde fin doping profile (such that the channel region is lightly doped while the base region is heavily doped), which can be achieved using oxygen insertion technology, are quantified through three-dimensional (3-D) simulations, for low-power FinFET technology at the 8/7nm node. As the transistor gate length is scaled down, variability in transistor threshold-voltage (Vt) increases; this hinders reductions in operating voltage, particularly for large arrays of six-transistor (6T) static memory (SRAM) cells. 3-D device simulations are performed using Sentaurus Device to investigate systematic sources and random sources of Vt variation, for both SSR FinFET and control FinFET devices. A compact analytical current-voltage (I-V) model calibrated to the 3-D device simulations is used to estimate 6T-SRAM cell yield and minimum operating voltage, to quantify the benefit of oxygen insertion technology for voltage scaling.