Millimeter-wave and sub-terahertz frequency bands are available for wideband applications such as high data-rate communication systems. As the respective wavelength is on the order of a millimeter, a compact on-chip antenna can be designed, thereby reducing the overall form factor and obviating expensive off-chip packaging. However, the channel propagation loss increases significantly with the frequency. Although CMOS technology is prevalent in digital processing and data communication, CMOS devices are lossy and inefficient at such high frequencies. Thus, it is challenging to implement an efficient and wideband transceiver at sub-terahertz frequencies using CMOS technology.

The aim of this dissertation is to demonstrate sub-terahertz wireless links for high-speed chip-to-chip communication in CMOS. First, transceiver architectures and building blocks are discussed to address the challenges and limitations of the CMOS process. Two fully integrated CMOS transceivers, a 260 GHz OOK transceiver and a 240 GHz QPSK/BPSK transceiver, are then demonstrated using on-chip antennas. Frequency multiplication and mixer-first design are employed to operate beyond the cut-off frequency. In the QPSK modulation, a maximum data rate of 16 Gbps is realized with an energy efficiency of 30 pJ/bit.

These demonstrations show that millimeter-wave/sub-terahertz wireless communication can be a promising solution for high-speed chip-to-chip communication. Improvements in the energy efficiency and silicon area of these wireless links can result in replacing or complementing existing wired links.