The aim of this dissertation is to demonstrate sub-terahertz wireless links for high-speed chip-to-chip communication in CMOS. First, transceiver architectures and building blocks are discussed to address the challenges and limitations of the CMOS process. Two fully integrated CMOS transceivers, a 260 GHz OOK transceiver and a 240 GHz QPSK/BPSK transceiver, are then demonstrated using on-chip antennas. Frequency multiplication and mixer-first design are employed to operate beyond the cut-off frequency. In the QPSK modulation, a maximum data rate of 16 Gbps is realized with an energy efficiency of 30 pJ/bit.
These demonstrations show that millimeter-wave/sub-terahertz wireless communication can be a promising solution for high-speed chip-to-chip communication. Improvements in the energy efficiency and silicon area of these wireless links can result in replacing or complementing existing wired links.